Thanks to Moore’s Law is Dead’s Tom, we have some information about the future of the EPYC implementation of the Zen6 architecture. AMD has not yet clarified whether it plans to continue using the Zen name for its future architecture. The information has been checked for errors and so far is claimed to be authentic. What AMD will do in the future, however, remains a question mark and there is a possibility that it may reverse its plans.
AMD’s 3rd generation EPYC update has also been released. The update comes with 3D V-Cache as we have already learned. Interestingly, the EPYC series we talked about earlier will make its debut three generations later. This series is codenamed “Venice” and will feature the Zen6 architecture. Considering this, we could see Venice sometime around 2024.
The video highlights some of the features of the EPYC Venice, including the all-new redesigned L2/L3 caches and the heavy reliance on the HBM implementations. By the time Venice is released, AMD will most likely resort to some other latest technology, such as using the 3D die. We get a pretty interesting combination of the large L3 caches working alongside the HBM memory.
As far as specs go, there isn’t much about the Zen6 as far as we know, other than it may use a new socket and support faster DDR5 memory variants. In comparison: this might be even faster than Turin.